ICS8516 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 4D. LVDS DC CHARACTERISTICS, V_DD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
V_OD
Δ V_OD
V_OS
Δ V_OS
I_OZ
I_OFF
I_OSD
I_OS/I_OSB
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Minimum
250
1.125
-10
-1
Typical
400
1.4
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
TABLE 5. AC CHARACTERISTICS, V_DD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
700
1.6
2.0
2.4
90
tsk(pp) Part-to-Part Skew; NOTE 3, 4
500
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Integration Range:
12kHz - 20MHz
148
t /t
Output Rise/Fall Time
RF
odc
Output Duty Cycle
20% to 80%
100
550
45
50
55
t_PZL, t_PZH Output Enable Time; NOTE 5
5
t_PLZ, t_PHZ Output Disable Time; NOTE 5
5
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Units
MHz
ns
ps
ps
fs
ps
%
ns
ns
8516FY
www.icst.com/products/hiperclocks.html
5
REV. B FEBRUARY 21, 2006