ICS844001I Datasheet, PDF (5/10 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844001I
FEMTOCLOCKS™CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
POWER SUPPLY
+ Float GND -
LVDS
Qx ^SCOPE
nQx
2.5V±5%
POWER SUPPLY
+ Float GND -
LVDS
Qx ^SCOPE
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Phase Noise Mask
f₁ ^{Offset Frequency} f₂
RMS Jitter = Area Under the Masked Phase Noise Plot
nQ
Q
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
RMS PHASE JITTER
Clock
20%
Outputs
80%
t_R
80%
t_F
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VV_DD_DD
out
V_{SW I N G}
DC Input LVDS
20%
out
➤
V_OS/Δ V_OS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
V^V_DD_DD
DC Input LVDS
out
➤
100
V_OD/Δ V_OD
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844001AGI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 16, 2005