ICS60101 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – LOW PHASE NOISE CLOCK MULTIPLIER

ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Parameter
Symbol Conditions
Operating Supply Current
IDD No load, 125 MHz
Short Circuit Current
Each output
Input Capacitance
C_IN OE, select pins
Note 1: Switching occurs nominally at VDD/2
Min.
±40
Typ.
22
±60
5
Max.
30
Units
mA
mA
pF
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
Fin
10
27
MHz
Output Frequency
at 3.3V or 5V
156 MHz
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
t_OR 0.8 to 2.0V no load
t_OF 0.8 to 2.0V, no load
at VDD/2
1.5
ns
1.5
ns
45
50
55
%
Maximum Absolute jitter, short
term, 125 MHz
No load
±50 ±75
ps
Maximum jitter, one sigma,
125 MHz (x5)
No load
12
20
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
-90 -94
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
1 kHz
-116 -120
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
-118 -122
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
100 kHz offset
-115 -119
dBc/Hz
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x,
maximum input frequency is 13.75 MHz).
MDS 601-01 L
5
Revision 111204
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