ICS16859 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

ICSSSTV16859
Timing Requirements¹
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
V_DDQ = 2.5V ± 0.2V
MIN
MAX
f_clock
t_PD
Clock frequency
Clock to output time
TSSOP
VFQFN (MLF2)
200
1.7
2.7
1.6
2.6
t_RST Reset to output time
5
t_SL Output slew rate
1
4
t_S
Setup time, fast slew rate ^{2 & 4}
Setup time, slow slew rate ^{3 & 4}
Data before CLK↑ , CLK#↓
0.60
0.80
T_h
Hold time, fast slew rate ^{2 & 4}
Hold time, slow slew rate ^{3 & 4}
Data after CLK↑ , CLK#↓
0.40
0.50
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of ≥ 1V/ns.
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
UNITS
MHz
ns
ns
ns
V/ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
SYMBOL
From
(Input)
To
(Output)
V_DD = 2.5V ±0.2V
UNITS
MIN TYP MAX
f_max
t_PD
CLK, CLK# (TSSOP)
CLK, CLK# (VFQFN[MLF2])
Q
Q
200
MHz
1.7
2.3
2.7
ns
1.6
2.1
2.6
ns
t_phl RESET#
Q
5
ns
0003G—05/21/02
5