ICS16859 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

ICSSSTV16859
General Description
The 13-bit-to-26-bit ICSSSTV16859 is a universal bus driver designed for 2.3V to 2.7V V_DD operation and
SSTL_2 I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The
positive edge of CLK is used to trigger the data flow whereas CLK# is used to maintain sufficient noise margins
where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only.
ICSSSTV16859 supports low-power standby operation. A logic level “Low” at RESET# assures that all internal
registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/
CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid
logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be
held at a logic “low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and
CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative
to the time to disable the differential input receivers. This ensures there are no glitches on the output. However,
when coming out of low-power standby state, the register will become active quickly relative to the time to
enable the differential input receivers. When the data inputs are at a logic level “low” and the clock is stable
during the “Low”-to-”High” transition of RESET# until the input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
Pin Configuration (64-Pin TSSOP)
PIN NUMBER
1-5, 8-14, 16, 17, 19-25, 28-32
PIN NAME
Q (13:1)
TYPE
OUTPUT
7, 15, 26, 34, 39, 43, 50, 54,
58, 63
6, 18, 27, 33, 38, 47, 59, 64
35, 36, 40-42, 44, 52, 53, 55-
57, 61, 62
GND
VDDQ
D (13:1)
PWR
PWR
INPUT
48
49
37, 46, 60
CLK
CLK#
VDD
INPUT
INPUT
PWR
51
RESET#
INPUT
45
VREF
INPUT
Pin Configuration (56-Pin MLF2)
PIN NUMBER
1-8, 10-16, 18-22, 50-54, 56
37, 48
9, 17, 23, 27, 34, 44, 49, 55
24, 25, 28-31, 39-43, 46, 47
35
36
26, 33, 45
38
32
-
PIN NAME
Q (13:1)
GND
VDDQ
D (13:1)
CLK
CLK#
VDD
RESET#
VREF
Center PAD
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
PWR
0003G—05/21/02
Data output
DESCRIPTION
Ground
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
DESCRIPTION
Data output
Ground
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
Ground (MLF2 package only)
2