8T49N285 Datasheet, PDF (43/65 Pages) Integrated Circuit Systems – Open-drain Interrupt pin

8T49N285 DATA SHEET
Table 12. PCI Express Jitter Specifications, V_CC = 3.3V ±5% or 2.5V ±5%, V_CCOx = 3.3V ±5% or 2.5V ±5%,
T_A = -40°C to 85°C^{1, 2}
Symbol
Parameter
Test Conditions
PCIe Industry
Minimum Typical Maximum Specification
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak
345
ƒ= 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (clock frequency/2)
8
16
86
Units
ps
t_{REFCLK_HF_RMS} Phase Jitter RMS
ƒ= 100MHz, 40MHz Crystal Input,
(PCIe Gen 2) ^{4 5 6}
High Band: 1.5MHz - Nyquist (clock frequency/2)
0.8
1.8
3.1
ps
t_{REFCLK_LF_RMS} Phase Jitter RMS 
(PCIe Gen 2) ^{4 5 6}
ƒ= 100MHz, 40MHz Crystal Input,
Low Band: 10kHz - 1.5MHz
0.03
0.5
3.0
ps
t_{REFCLK_RMS}
(PCIe Gen 3)
Phase Jitter RMS
ƒ= 100MHz, 40MHz Crystal Input,
457
Evaluation Band: 0Hz - Nyquist (clock frequency/2)
0.2
0.5
0.8
ps
NOTE 1: V_CCOx denotes V_CCO0, V_CCO1, V_CCO2, V_CCO3, V_CCO4, V_CCO5, V_CCO6, V_CCO7.
NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production
NOTE 5: Outputs configured for HCSL mode. Fox 277LF-40-18 crystal used with doubler logic enabled.
NOTE 6: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_REF-
CLK_HF_RMS ^{(High Band) and 3.0ps RMS for t}REFCLK_LF_RMS ^{(Low Band).}
NOTE 7: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Ex-
press Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specifica-
tion.
REVISION 3 06/29/15
43
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR