8T49N285 Datasheet, PDF (11/65 Pages) Integrated Circuit Systems – Open-drain Interrupt pin

8T49N285 DATA SHEET
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I²C compatible configuration to allow access to any of the
internal registers for device programming or examination of internal
status. All registers are configured to have default values. See the
specifics for each register for details.
The device has the additional capability of becoming a master on the
I²C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I²C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I²C bus or pre-programmed into the device prior
to assembly.
I²C Mode Operation
The I²C interface is designed to fully support v1.2 of the I²C
Specification for Normal and Fast mode operations. The device acts
as a slave device on the I²C bus at 100kHz or 400kHz using the
address defined in the Serial Interface Control register (0006h), as
modified by the S_A0 input pin setting. The interface accepts
byte-oriented block write and block read operations. Two address
bytes specify the register address of the byte position of the first
register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I²C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k typical.
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
A
P
Sequential Read
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
Sequential Write
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Data 0
A
Data 1
A
A
Data 1
A
A
A
Data n
A
P
Data n
A
P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 3. I²C Slave Read and Write Cycle Sequencing
I²C Master Mode
When operating in I²C mode, the 8T49N285 has the capability to
become a bus master on the I²C bus for the purposes of reading its
configuration from an external I²C EEPROM. Only a block read cycle
will be supported.
As an I²C bus master, the 8T49N285 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (E0h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I²C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N285 will not support the following functions:
• I²C General Call
• Slave clock stretching
• I²C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I²C devices including the external EEPROM
used for booting
REVISION 3 06/29/15
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