ICS9DB401 Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – Four Output Differential Buffer for PCI Express

Integrated
Circuit
Systems, Inc.
ICS9DB401
General Description
The ICS9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC
clocks. The ICS9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the
ICS952601, ICS954101 or ICS954201. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew
(50ps) requirements.
Block Diagram
4
OE(3:0)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
U
STOP
X
LOGIC
DIF(3:0))
PD
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
Power Groups
Pin Number
VDD
GND
1
4
5,11,18, 24
4
N/A
27
28
27
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
1014B—09/07/06
4