ICS9DB401 Datasheet, PDF(12/16 Page) Integrated Circuit Systems – Four Output Differential Buffer for PCI Express

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ICS9DB401 Datasheet, PDF (12/16 Pages) Integrated Circuit Systems – Four Output Differential Buffer for PCI Express

◁

Integrated

Circuit

Systems, Inc.

ICS9DB401

Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.

SRC_STOP#

The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must

be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two

consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.

SRC_STOP# - Assertion (transition from '1' to '0')

Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output

to stop). When the SRC_STOP# drive bit is â0â, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There

is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the

SRC_STOP# drive bit is â1â, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.

SRC_STOP# - De-assertion (transition from '0' to '1')

All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is

2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is â1â (tri-state), all

stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.

SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)

1mS

SRC_Stop#

PWRDWN#

DIF (Free Running)

DIF# (Free Running)

DIF (Stoppable)

DIF# (Stoppable)

SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)

1mS