ICS9248-141 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – AMD - K7™ System Clock Chip

ICS9248-141
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit Bit Bit Bit Bit CPUCLK
PCICLK
27654
(MHz)
(MHz)
00000
90.00
30.00
0000 1
95.00
31.67
000 10
101.00
33.67
000 11
102.00
34.00
00 100
100.90
33.57
00 10 1
103.00
34.33
00 110
105.00
35.00
00 111
100.00
33.33
0 1000
107.00
35.67
0 100 1
109.00
36.33
0 10 10
110.00
36.67
0 10 11
111.00
37.00
0 1100
113.00
37.67
0 110 1
115.00
38.33
0 1110
117.00
39.00
0 1111
133.30
33.33
10 0 0 0
120.00
40.00
1000 1
125.00
31.25
100 10
130.00
32.50
100 11
133.73
33.43
10 100
135.00
33.75
10 10 1
137.00
34.25
10 110
139.00
34.75
10 111
100.00
33.33
1 10 0 0
140.00
35.00
1100 1
143.00
35.75
110 10
145.00
36.25
110 11
148.00
37.00
1 1 10 0
150.00
37.50
1110 1
155.00
38.75
1 1 1 10
166.66
41.67
11111
133.33
33.33
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ±0.25% Center Spread
0 - Running
1- Tristate all outputs
Spread
Precentage
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
PWD
Reserved
0
1
0
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