ICS9248-131 Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248 - 131
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit7 Bit2 Spread Spectrum Method
0,0
+/- 0.25% Center Spread Spectrum Modulation
Bit 7,2
0,1
+/- 0.15% Center Spread Spectrum Modulation
1,0
0 to -0.5 Down Spread Spectrum Modulation
1,1
+/- 0.375% Center Spread Spectrum Modulation
Bit6 Bit5 Bit4 CPU Clock
PCI
AGP
111
100
33.33
66.67
110
95.25
31.75
63.50
101
83.3
33.30
66.60
Bit 6:4
100
97
32.33
64.66
011
91.5
30.50
61.00
010
96.22
32.07
64.15
001
66.67
33.33
66.67
000
60
30.00
60.00
Bit 3 ^{0 - Frequency is selected by hardware select, Latched inputs}
1 - Frequency is selected by Bit 6:4 (above)
Bit 1 ^{0 - Normal}
1 - Spread Spectrum Enabled
Bit 0 ^{0 - Running}
1 - Tristate all outputs
PWD
0,0
Note1
001
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 001, and if bit
3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
X
X
1
1
1
1
1
Description
(Reserved)
FS2#
FS1#
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
X
1
X
1
1
1
1
1
Description
CPU2.5_3.3#
PCICLK_F (Act/Inact)
FS0#
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
I²C is a trademark of Philips Corporation
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