ICS9248-131 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248 - 131
Pin Descriptions
PIN NUMBER
1, 6, 14, 19,
30, 36, 48
2
3,9,16,22,27,
33,39,45
4
PIN NAME
VDD
REF0
CPU2.5_3.3#^1,2
GND
X1
5
X2
7
8
13, 12, 11, 10
15
PCICLK_F
FS1^{1, 2}
PCICLK0
FS2^{1, 2}
PCICLK(4:1)
BUFFERIN
17
18
40, 28, 29, 31, 32,
34, 35, 37, 38
20
21
23
24
25
26
CPU_STOP#¹
SDRAM 11
PCI_STOP#¹
SDRAM 10
SDRAM (12, 7:0)
AGP_STOP#
SDRAM9
PD#
SDRAM8
SDATA
SCLK
AGP_F
MODE^{1, 2}
48MHz
FS0^{1, 2}
41, 43, 44
42
46, 47
CPUCLK(2:0)
VDDL
AGP (1:0)
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
OUT
IN
PWR
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
OUT
IN
OUT
IN
OUT
PWR
OUT
14.318 Mhz reference clock.
Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU¹. Latched input²
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
Has internal load cap (33pF)
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Input pin for SDRAM buffers.
Halts CPUCLK clocks at logic 0 level,
when input low (in Mobile Mode, MODE=0)
SDRAM clock output
Halts PCICLK clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
SDRAM clock output
SDRAM clock outputs.
This asynchronous input halts AGP clocks at logic "0" level when input low
(in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
Advanced Graphic Port output, Not affected by AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL. Low if CPU_STOP#=Low
Supply for CPU, either 2.5V or 3.3V nominal
Advanced Graphic Port outputs
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2