ICS9147-03 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for 686 Series CPUs

ICS9147- 03
Electrical Characteristics at 3.3V
V_DD = 3.0 – 3.7V, T_A = 0 – 70° C unless otherwise stated
AC Characteristics
PARAMETER
Rise Time¹
Fall Time¹
Rise Time¹
Fall Time¹
Rise Time¹
Fall Time¹
Rise Time¹
Fall Time¹
Duty Cycle¹
Jitter, One Sigma¹
Jitter, Absolute¹
Jitter, One Sigma¹
Jitter, Absolute¹
Input Frequency¹
Logic Input Capacitance¹
Crystal Oscillator Capacitance¹
Power-on Time¹
Clock Skew¹
Clock Skew¹
Clock Skew¹
Clock Skew¹
SYMBOL
T_r1
T_f1
T_r2
T_f2
T_r3
T_f3
T_r4
T_f4
D_t
T_jis1
T_jab1
T_jis2
T_jab2
F_i
C_IN
C_INX
t_on
T_sk1
T_sk2
T_sk3
T_SR4
TEST CONDITIONS
20pF load, 0.8 to 2.0V
CPU, SDRAM, BUS & REF
20pF load, 2.0 to 0.8V
CPU, SDRAM, BUS & REF
20pF load, 20% to 80%
CPU, SDRAM, BUS & REF
20pF load, 80% to 20%
CPU, SDRAM, BUS & REF
20pF load, 0.8 to 2.0V
fixed 24 & 48 clocks
20pF load, 2.0 to 0.8V
fixed 24 & 48 clocks
20pF load, 0.4 to 2.0V , CPUL with
VDDL = 2.5V
20pF load, 2.0 to 0.4V, CPUL with
VDDL = 2.5V
20pF load @ VOUT=1.4V
CPU & BUS Clocks; Load=20pF,
SDRAM; Load = 30pF
25 MHz, BSEL=1
CPU & BUS Clocks; Load=20pF,
SDRAM; Load = 30pF
FOUT=25 MHz, BSEL=1
Fixed CLK; Load=20pF
Fixed CLK; Load=20pF
Logic input pins
X1, X2 pins
From VDD=1.6V to 1st crossing of 66.6
MHz VDD supply ramp < 40ms
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
BUS to BUS; Load=20pF; @1.4V
CPU to BUS; Load=20pF; @1.4V
(CPU is early)
SDCPU (@3.3V) to CPU (@2.5V)
(2.5V CPU is late)
MIN
-
-
-
-
-
-
-
-
45
-
-250
-
-5
12.0
-
-
-
-
-
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
TYP
MAX
0.9
1.5
0.8
1.4
1.5
2.5
1.4
2.4
1.7
2.5
1.2
2.0
2.0
3.0
1.5
2.5
50
55
50
150
-
250
1
3
2
5
14.318
16.0
5
-
18
-
2.5
4.5
150
250
300
500
2.6
4
250
400
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
%
ps
ps
%
%
MHz
pF
pF
ms
ps
ps
ns
ps
4