ICS9147-03 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for 686 Series CPUs

ICS9147- 03
Functionality with (14.31818 MHz input)
Address Select
CPUL (1:2)
CPUH
SDRAM
(1:12)
BUS (1:6)
(MHz)
24M 48M
(MHz) (MHz)
FS2 FS1 FS0 (MHz) BSEL=1 BSEL=0 (MHz) (MHz)
000
60
30
32
24
48
001
66.8
33.4
32
24
48
0 10
50
25
32
24
48
011
55
27.5
32
24
48
100
75
37.5
32
24
48
10 1
68.5
34.3
32
24
48
1 1 0 Test/2** Test/4** Test/3** Test/4** Test/2**
111
Tristate Tristate Tristate Tristate Tristate
**Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock
overriding crystal at X1 pin.
SDRAM Clock Enable
STP2# STP3#
0
0
0
1
1
0
1
1
DIMM
BANK1
SDRAM
(1:4)
ON
ON
ON
ON
DIMM
BANK2
SDRAM
(5:8)
Stopped
Low
Stopped
Low
ON
ON
DIMM
BANK3
SDRAM
(9:12)
Stopped
Low
ON
Stopped
Low
ON
Pin Descriptions
PIN NUM BER
2
3, 9, 16, 22,
27, 33, 39, 45
4
5
41
8, 10, 11, 12, 14,
15
PIN NAM E
REF
FS1
GND
X1
X2
VDDL
BUS (1:5)
BUS6
FS0
23, 24
STP# (2:3)
47
1, 6, 13, 19,
30, 36, 48
17, 18, 20, 21, 28,
29, 31, 32, 34,
35, 37, 38
40
42, 43
7, 25, 26
46
44
24M
BSEL
VDD3
SDRAM (1:12)
CPUH/AGP
CPUL (1:2)
N/C
48M
FS2
IO AP IC
TYPE
O UT
IN
PWR
IN
O UT
PWR
O UT
OUT
IN
IN
O UT
IN
PWR
D ES CR IPTION
Reference clock output*
Logic input frequency select Bit1*. Input latched at Poweron.
Ground.
Crystal input. Nominally 14.318 MHz. Has internal load cap
Crystal output. Has internal load cap and feedack resistor to X1
2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers.
BUS clock outputs. see select table for frequency
BUS clock output. See select table for frequency.*
Logic input frequency select Bit0.*. Input latched at Poweron.
Bank enable solutions for SDRAM clocks see table above, Clocks are
enabled in groups of 4. (STP2# stops DIMM bank2, STP3# stops DIMM
bank 3 when low).
24MHz fixed clock.*
Logic input* for selecting synchronous or asynchronous BUS frequency-
see table above. Input latched at Poweron.*
3.3 volt core logic and buffer power
OUT SDRAM clocks at CPU speed. See select table for frequency.
O UT
O UT
—
O UT
IN
O UT
CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc.
CPU clock output clocks .See select table for frequency. Operates at
down to 2.5V controlled by VDDL pin.
Pins not internally connected.
48 MHz fixed clock output*.
Logic input frequency select Bit 2*. Input latched at Poweron.
Reference clock (14.318MHz) powered by VDDL,
operating 2.5 to 3.3V.
* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2