ICS85320I Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR

Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
TABLE 4A. AC CHARACTERISTICS, V_CC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_PD
tjit
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Part-to-Part Skew; NOTE 2, 3
ƒ ≤ 267MHz
Integration Range:
12KHz - 20MHz
267
MHz
0.8
1.4
ns
0.05
ps
275
ps
t_R, t_F
Output Rise/Fall Time
odc
Output Duty Cycle
20% to 80%
200
45
700
ps
55
%
NOTE 1: Measured from V_CC/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, V_CC = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
t
Propagation Delay; NOTE 1
PD
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
ƒ ≤ 267MHz
Integration Range:
12KHz - 20MHz
215
MHz
0.8
1.7
ns
0.05
ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3
375
ps
t_R, t_F
Output Rise/Fall Time
odc
Output Duty Cycle
20% to 80%
200
45
700
ps
55
%
NOTE 1: Measured from V /2 point of the input to the differential output crossing point.
CC
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85320AMI
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4
REV. A AUGUST 25, 2004