ICS853111-01 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
TABLE 3C. ECL POWER SUPPLY DC CHARACTERISTICS, V_CC = 0V; V_EE = -3V TO -3.8V
Symbol Parameter
Test Conditions
Minimum
V_EE
Supply Voltage
-3.0
I_EE
Power Supply Current
Typical
-3.3
55
Maximum
-3.8
Units
V
mA
Table 3D. ECL DC Characteristics, V_CC = 0V; V_EE = -3V to -3.8V
Symbol Parameter
-40°C
Min Typ Max
25°C
Min Typ Max
85°C
Units
Min Typ Max
V
OH
V_OL
V_IH
V_IL
V_BB
V
PP
V_CMR
I_IH
Output High Voltage; NOTE 1
-1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V
Output Low Voltage; NOTE 1
-1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V
Input High Voltage(Single-Ended)
-1.225
-0.94 -1.225
-0.94 -1.225
-0.94 V
Input Low Voltage(Single-Ended)
-1.87
-1.535 -1.87
-1.535 -1.87
-1.535 V
Output Voltage Reference; NOTE 2 -1.44
-1.32 -1.44
-1.32 -1.44
-1.32 V
Peak-to-Peak Input Voltage
150
800 1200 150
800 1200 150
800 1200 V
Input High Voltage
Common Mode Range; NOTE 3, 4
V_EE+1.2V
0 V_EE+1.2V
0 V_EE+1.2V
0
V
Input
High Current
PCLK, nPCLK
150
150
150 µA
I_IL
Input
Low Current
PCLK, nPCLK
-150
-150
-150
µA
Input and output parameters vary 1:1 with V_CC. V_EE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to V_CCO - 2V.
NOTE 2: Single-ended input operation is limited. V_CC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V_IH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V_CC + 0.3V.
TABLE 4. AC CHARACTERISTICS, V_CC = 3V TO 3.8V; V_EE = 0V OR V_CC = 0V; V_EE = -3V TO -3.8V
Symbol Parameter
-40°C
25°C
85°C
Units
Min Typ Max Min Typ Max Min Typ Max
f_MAX
tp_LH
tp_HL
tsk(o)
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 4
>2
>2
>2
GHz
350 500 650 385 525 675 410 350 700 ps
450 600 750 480 620 760 515 650 785 ps
20 35
20 35
20 35 ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
200
0.03
200
0.03
200 ps
0.03
ps
t_R/t_F
Output Rise/Fall Time 20% to 80% 90 200 315 100 203 310 95 210 300 ps
All parameters measured at f ≤ 1GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111AV-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
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