ICS8442 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
H
X
X
Inputs
N S_LOAD
X
X
S_CLOCK
X
S_DATA
X
Conditions
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but
does not effect loaded M, N, and T values.
L
L
Data Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
XX
↓
L
Data M divider and N output divider values are latched.
L
H
XX
L
X
X Parallel or serial input do not affect shift registers.
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
250
10
0
0
0
0
0
1
0
1
0
275
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
700
28
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N1
N0
0
0
0
1
1
0
1
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum Maximum
250
700
125
350
62.5
175
31.25
87.5
8442AY
www.icst.com/products/hiperclocks.html
4
REV. C JULY 8, 2004