ICS8442 Datasheet, PDF (3/15 Pages) Integrated Circuit Systems – 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown ^{of nP_LOAD input. LVCMOS / LVTTL interface levels.}
Input
Pulldown
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
7
nc
Unused
No connect.
8, 16
GND
Power
Power supply ground.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
10, 13
11, 12
V_DD
Power
FOUT1, nFOUT1 Output
Core supply pins.
Differential output for the synthesizer. LVDS interface levels.
14, 15 FOUT0, nFOUT0 Output
Differential output for the synthesizer. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not effect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
21
V_DDA
Power
Analog supply pin.
Selects between crystal oscillator or test inputs as the PLL reference
22
XTAL_SEL
Input Pullup source. Selects XTAL inputs when HIGH. Selects TEST_CLK when
LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24, 25 XTAL1, XTAL2 Input
Crystal oscillator interface. XTAL1 is the input XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8442AY
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3
REV. C JULY 8, 2004