ICS844021I-01 Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3D. LVDS DC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Differential Output Voltage
Δ
V
OD
V_OD Magnitude Change
V_OS
Offset Voltage
Δ V_OS
V_OS Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
Typical
400
40
1.3
50
Maximum
Units
mV
mV
V
mV
TABLE 3E. LVDS DC CHARACTERISTICS, V_DD = V_DDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V
Differential Output Voltage
OD
Δ V_OD
V_OD Magnitude Change
V_OS
Offset Voltage
Δ V_OS
V_OS Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
Typical
400
40
1.2
50
Maximum
Units
mV
mV
V
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
24.5
34
50
7
1
Units
MHz
Ω
pF
mW
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
125MHz @ Integration Range:
1.875MHz - 20MHz
133.33MHz @ Integration Range:
1.875MHz - 20MHz
166.66MHz @ Integration Range:
1.875MHz - 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
Minimum Typical Maximum Units
122.5
170
MHz
0.45
ps
TBD
ps
TBD
ps
300
ps
50
%
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
125MHz @ Integration Range:
1.875MHz - 20MHz
133.33MHz @ Integration Range:
1.875MHz - 20MHz
166.66MHz @ Integration Range:
1.875MHz - 20MHz
122.5
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
NOTE 1: Please refer to the Phase Noise Plots following this section.
844021AGI-01
www.icst.com/products/hiperclocks.html
Typical
0.45
TBD
TBD
320
50
Maximum Units
170
MHz
ps
ps
ps
ps
%
REV. A MARCH 29, 2005
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