ICS840002-32 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840002-32
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
212.5
f_OUT
Output Frequency Range
106.25
75
tsk(o) Output Skew; NOTE 1, 3
TBD
212.5MHz @ Integration Range:
2.55MHz - 20MHz
0.50
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
106.25MHz @ Integration Range:
637kHz - 5MHz
0.86
75MHz @ Integration Range:
12kHz - 20MHz
TBD
t_R / t_F
Output Rise/Fall Time
20% to 80%
400
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
Units
MHz
ps
ps
ps
ps
ps
%
TABLE 5B. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
212.5
MHz
f_OUT
Output Frequency Range
106.25
75
tsk(o) Output Skew; NOTE 1, 3
TBD
ps
212.5MHz @ Integration Range:
2.55MHz - 20MHz
0.57
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
106.25MHz @ Integration Range:
637kHz - 5MHz
1.1
ps
75MHz @ Integration Range:
12kHz - 20MHz
TBD
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
ps
50
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840002BG-32
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4
REV. A JUNE 27, 2005