ICS83115 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V_DD = 3.3V±5%, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_pLH
tjit(Ø)
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
IJ 200MHz
Integration Range:
12KHz - 20MHz
200
MHz
1.7
2.4
3.1
ns
0.09
ps
tsk(o) Output Skew; NOTE 2, 4
Measured on rising edge @V_DD/2
150
250
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
Measured on rising edge @V_DD/2
800
ps
t_R / t_F
Output Rise/Fall Time
20% to 80%
650
1150
ps
odc
Output Duty Cycle
45
55
%
t_EN
Output Enable Time
20
ns
t_DIS
Output Disable Time
20
ns
All parameters measured at f unless noted otherwise.
MAX
NOTE 1: Measured from V_DD/2 of the input to V_DD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DD/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V_DD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83115BR
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4
REV. A SEPTEMBER 21, 2004