ICS83115 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83115
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
OE1
Input
2, 3, 4, 7,
8, 11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7,
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
Output
Pullup
Output enable. When LOW, forces outputs Q2 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
5, 6, 23, 24
9, 10, 19, 20
V_DD
GND
Power
Power
Core supply pin.
Power supply ground.
14
IN
Input Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
15
OE0
Input
Pullup
Output enable. When LOW, forces outputs Q8 thru Q13 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
28
OE2
Input
Pullup
Output enable. When LOW, forces outputs Q0, Q1, Q15 and Q14 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C
PD
R_PULLUP
R_PULLDOWN
R_OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V = 3.465V
DD
V_DD = 3.3V
Minimum Typical Maximum Units
4
pF
11
pF
51
KΩ
51
KΩ
5
7
12
Ω
TABLE 3. FUNCTION TABLE
Inputs
OE0
OE1
OE2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NOTE: OE0:OE2 are 5V tolerant.
Q0, Q1, Q14, Q15
(Control OE2)
HiZ
Active
HiZ
Active
HiZ
Active
HiZ
Active
Outputs
Q2:Q7
(Control OE1)
HiZ
HiZ
Active
Active
HiZ
HiZ
Active
Active
Q8:Q13
(Control OE0)
HiZ
HiZ
HiZ
HiZ
Active
Active
Active
Active
83115BR
www.icst.com/products/hiperclocks.html
2
REV. A SEPTEMBER 21, 2004