ICS601-01 Datasheet, PDF (4/5 Pages) Integrated Circuit Systems – Low Phase Noise Clock Multiplier

ICS601-01
Low Phase Noise Clock Multiplier
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
Ambient Operating Temperature, I version
Industrial temperature
Soldering Temperature
Max of 10 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1/ICLK pin only Note 3
Input Low Voltage, VIL, X1/ICLK pin only
Note 3
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
IOH=-4mA
Output High Voltage, VOH
IOH=-12mA
Output Low Voltage, VOL
IOL=12mA
Operating Supply Current, IDD
No Load, 125 MHz
Short Circuit Current
Each output
Input Capacitance
OE, select pins
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Frequency
Output Frequency
at 3.3V or 5V
Output Clock Rise Time
0.8 to 2.0V, no load
Output Clock Fall Time
0.8 to 2.0V, no load
Output Clock Duty Cycle
At VDD/2
Maximum Absolute Jitter, short term, 125 MHz No load, REF off
Maximum Jitter, one sigma, 125 MHz (x5)
No load, REF off
Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset
Phase Noise, relative to carrier, 125 MHz (x5) 1 kHz offset
Phase Noise, relative to carrier, 125 MHz (x5) 10 kHz offset
Phase Noise, relative to carrier, 125 MHz (x5) 100 kHz offset
Minimum
-0.5
0
-40
-65
3.0
(VDD/2)+1
2
VDD-0.4
2.4
±40
10
45
-105
-120
-128
-121
Typical
22
±60
5
50
±50
18
-108
-123
-132
-125
Maximum Units
7
V
VDD+0.5
V
70
°C
85
°C
260
°C
150
°C
5.5
V
V
(VDD/2)-1 V
V
0.8
V
V
V
0.4
V
30
mA
mA
pF
27
MHz
156
MHz
1.5
ns
1.5
ns
55
%
±75
ps
25
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. The phase relationship between input and output can change at power up. For a fixed phase relationship, see the ICS570
or ICS670.
3. Switching occurs nominally at VDD/2.
MDS 601-01 G
4
Revision 090800
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• [phone]tel • www.icst.com