ICS601-01 Datasheet, PDF (3/5 Pages) Integrated Circuit Systems – Low Phase Noise Clock Multiplier

ICS601-01
Low Phase Noise Clock Multiplier
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that
can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will increase the
phase noise, so it is important to have a stable, low noise supply voltage at the device. Use decoupling
capacitors of 0.1 µF in parallel with 0.01 µF. It is important to have these capacitors as close as possible to
the ICS601-01 supply pins.
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this
can reduce the phase noise by as much as 10 dBc/Hz.
0
-20
-40
-60
-80
-100
-120
-140
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
Offset from Carrier (Hz)
1.0E+6
10.0E+6
Figure 1. Phase Noise of ICS601-01 at 125 MHz out, 25 MHz crystal input.
VDD = 3.3 V, REFOUT disabled.
External Components/Crystal Selection
The ICS601-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as
possible. A series termination resistor of 33 Ω may be used for each clock output. The crystal must be
connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do
not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1
to ground and X2 to ground. In general, the value of these capacitors is given by the following equation,
where C_L is the crystal load capacitance: Crystal caps (pF) = (C_L-5) x 2. So for a crystal with 16 pF load
capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board
capacitance and recommend the exact capacitance value to use.
MDS 601-01 G
3
Revision 090800
Printed 11/14/00
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