ICS2509C Datasheet, PDF (4/7 Pages) Integrated Circuit Systems – 3.3V Phase-Lock Loop Clock Driver

ICS2509C
Electrical Characteristics - Input & Supply
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V_IH
Input Low Voltage
V_IL
Input High Current
I_IH
V_IN = V_DD
Input Low Current
I_IL
V_IN = 0 V;
Operating current
I_DD1
C_L = 0 pF; F_IN @ 66M
Input Capacitance
Output Capacitance
C_IN1
Logic Inputs
C_O1
Logic Outputs
1_{Guarenteed by design, not 100% tested in production.}
MIN
2
V_SS-0.3
TYP MAX UNITS
V_DD+0.3 V
0.8
V
0.1 100 uA
19
50
uA
140 170 mA
4
pF
8
pF
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Symbol Parameter
Test Conditions
Min.
Max.
Unit
Fclk Input clock frequency
25
175
MHz
Input clock frequency
duty cycle
40
60
%
Stabilization time
After power up
1
ms
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not
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