ICS2509C Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – 3.3V Phase-Lock Loop Clock Driver

ICS2509C
Pin Descriptions
PIN NUM BER PIN NAM E
1
AGND
2, 10, 15 VCC
3
CLKA0
4
CLKA1
5
CLKA2
6, 7, 18, 19 GND
8
CLKA3
9
CLKA4
11
OEA¹
12
FBOUT
13
FB IN
14
OEB¹
16
CLKB3
17
CLKB2
20
CLKB1
21
CLKB0
22
VCC
23
AVCC
24
C L KIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
PWR
IN
IN
DE SC R IPT ION
Analog Ground
Power Supply (3.3V)
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, Bank A
Gro u n d
Buffered clock output, Bank A
Buffered clock output, Bank A
Output enable (has internal pull_up). When high, normal operation.
When low bank A clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Output enable (has internal pull_up). When high, normal operation.
When low bank B clock outputs are disabled to a logic low state.
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
OEA
0
0
1
1
INPUTS
OEB
0
1
0
1
AVCC
3 .3 3
3 .3 3
3 .3 3
3 .3 3
CLKA
(0 : 4 )
0
0
Dri v e n
Dri v e n
OUTPUTS
CLKB
(0 : 3 )
0
FBOUT
Dri v e n
Driven Driven
0
Dri v e n
Driven Driven
So u rc e
PLL
PLL
PLL
PLL
PLL
Shutdown
N
N
N
N
Buffer M ode
0
0
0
0
0
Driven CLKIN
Y
0
1
0
0
Driven Driven CLKIN
Y
1
0
0
Dri v e n
0
Driven CLKIN
Y
1
1
0
Driven Driven Driven CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers
2