8T49N241 Datasheet, PDF (4/64 Pages) Integrated Circuit Systems – Manual clock selection control input

8T49N241 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1
V_CCA
2
V_CCA
3
GPIO[0]
4
V_CCO0
5
Q0
6
nQ0
7
GPIO[1]
8
nQ1
9
Q1
10
V_CCO1
11
SDATA
12
SCLK
13
V_CC
14
V_EE
15
V_CC
16
CLK0
17
nCLK0
18
CLK1
19
nCLK1
20
S_A1
21
V_CCO2
22
Q2
23
nQ2
24
GPIO[2]
25
nQ3
26
Q3
27
V_CCO3
28
GPIO[3]
29
nINT
30
V_CCA
31
nRST
Type¹
Description
Power
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Power
Analog function supply for analog functions associated with the PLL. 2.5V or
3.3V supported.
I/O
Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
Power
High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
O
Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.
O
Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.
I/O
Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O
Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.
O
Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.
Power
I/O
I/O
Pullup
Pullup
High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
I²C interface bi-directional data.
I²C interface bi-directional clock.
Power
Core digital function supply. 2.5V or 3.3V supported.
Power
Negative supply voltage. All V_EE pins and EPAD must be connected before any
positive supply voltage is applied.
Power
Core digital function supply. 2.5V or 3.3V supported.
I
Pulldown Non-inverting differential clock input 0.
Pullup / Inverting differential clock input 0.
I
Pulldown V_CC / 2 when left floating (set by internal pullup / pulldown resistors)
I
Pulldown Non-inverting differential clock input 1.
Pullup / Inverting differential clock input 1.
I
Pulldown V_CC / 2 when left floating (set by internal pullup / pulldown resistors).
I
Pulldown I²C Address Bit A1
Power
High-speed output supply voltage for output pair Q2, nQ2. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
O
Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.
O
Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.
I/O
Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O
Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.
O
Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.
Power
High-speed output supply voltage for output pair Q3, nQ3. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
I/O
Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O
Open-drain _{Interrupt output.}
with pullup
Power
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
Master Reset input. LVTTL / LVCMOS interface levels:
I
Pullup
0 = All registers and state machines are reset to their default values
1 = Device runs normally
FEMTOCLOCK^®NG UNIVERSAL FREQUENCY TRANSLATOR
4
REVISION 1 08/07/15