8T49N241 Datasheet, PDF (32/64 Pages) Integrated Circuit Systems – Manual clock selection control input

8T49N241 DATA SHEET
Table 7R. Global Interrupt Status Register Bit Field Locations and Descriptions
Global Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
020D
Rsvd
Rsvd
Rsvd
020E
Rsvd
Rsvd
020F
Rsvd
Rsvd
0210
Rsvd
Rsvd
EEP_ERR
0211
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
0212
Rsvd
D0
INT
BOOTFAIL
EEPDONE
Bit Field Name
INT
EEP_ERR
BOOTFAIL
EEPDONE
Rsvd
Field Type
R/O
R/O
R/O
R/O
R/W
Global Interrupt Status Register Block Field Descriptions
Default Value Description
Device Interrupt Status:
-
0 = No Interrupt Status bits that are enabled are asserted (nINT pin released)
1 = At least one Interrupt Status bit that is enabled is asserted (nINT pin asserted low)
-
CRC Mismatch on EEPROM Read. Once set this bit is only cleared by reset.
-
Reading of Serial EEPROM failed. Once set this bit is only cleared by reset.
-
Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
FEMTOCLOCK^®NG UNIVERSAL FREQUENCY TRANSLATOR
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REVISION 1 08/07/15