8T49N286 Datasheet, PDF (34/78 Pages) Integrated Circuit Systems – Bypass clock paths for system tests

8T49N286 DATA SHEET
Bit Field Name Field Type
NS1_Qm[1:0]
(m = 0,1)
R/W
NS1_Qm[1:0]
(m = 4, 5, 6, 7)
R/W
NS2_Qm[15:0]
R/W
N_Qm[17:0]
R/W
NFRAC_Qm[27:0] R/W
Rsvd
R/W
Output Divider Control Register Block Field Descriptions
Default Value Description
1st Stage Output Divider Ratio for Output Clock Qm, nQm (m = 0,1):
00 = /5
10b
01 = /6
10 = /4
11 = Output Qm, nQm not switching
1st Stage Output Divider Ratio for Output Clock Qm, nQm (m = 4, 5, 6, 7):
00 = /5
10b
01 = /6
10 = /4
11 = /1 (Do not use this selection if PLL0 or PLL1 are the source since the 2nd-stage
divider has a limit of 1GHz).
0002h
2nd Stage Output Divider Ratio for Output Clock Qm, nQm (m = 0, 1, 4, 5, 6, 7):
Actual divider ratio is 2x the value written here.
A value of 0 in this register will bypass the second stage of the divider.
00008h
Integer Portion of Output Divider Ratio for Output Clock Qm, nQm (m = 2, 3):
Values of 0, 1 or 2 cannot be written to this register. Actual integer portion is 2x the
value written here.
0000000h
Fractional Portion of Output Divider Ratio for Output Clock Qm, nQm (m = 2, 3):
Actual fractional portion is 2x the value written here.
Fraction = (NFRAC_Qm * 2) * 2^-28
-
Reserved. Always write 0 to this bit location. Read values are not defined.
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
34
REVISION 5 07/08/15