8T49N286 Datasheet, PDF (13/78 Pages) Integrated Circuit Systems – Bypass clock paths for system tests

8T49N286 DATA SHEET
nCS
SCLK
Tsu1
Tsu2 Th2
Tpw2 Tpw1
SDI
R/W
A0
Td1
SDO
Hi-Z
Figure 5. SPI Read/Write Timing Diagram
Table 5. Timing Characteristics in SPI Mode
Symbol
Parameter
T
Internal timing parameter used to calculate SPI timing specs
t_su1
Valid nCS to SCLK rising setup time
t_su2
Valid SDI to SCLK rising setup time
t_d1
SCLK falling to valid data delay time
t_d2
nCS rising edge to SDO high impedance delay time
t_pw1
SCLK pulse width low
t_pw2
SCLK pulse width high
t_h1
Valid nCS after valid SCLK hold time
t_h2
Valid SDI after valid SCLK hold time
t_csh
Time between consecutive Read-Read or Read-Write accesses
(nCS rising edge to nCS falling edge)
NOTE: Specifications guaranteed by design and characterization.
Th1
Td2
Hi-Z
Min
Typ
Max
Unit
T = PLL0 period * 64
ns
2T
ns
5
ns
4T + 5
ns
15
ns
5T
ns
5T
ns
2T
ns
3T
ns
3T
ns
REVISION 5 07/08/15
13
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