ICS9DB106 Datasheet, PDF (3/9 Pages) Integrated Circuit Systems – 6 Output PCI Express Buffer with CLKREQ Function

Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
General Description
The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential
SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It
attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock
request (OE#) pins make the ICS9DB106 suitable for Express Card applications.
Block Diagram
CLKREQ1#
CLKREQ4#
CLK_INT
C LK_INC
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX1
PCIEX4
PCIEX(0,2,3,5)
IREF
Power Groups
Pin Number
VDD
GND
7, 13, 16, 22
8,21
TBD
TBD
N/A
27
28
27
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
0833A—07/26/04
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