ICS951411 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – System Clock Chip for ATI RS400 P4TM-based Systems

Integrated
Circuit
Systems, Inc.
ICS951411
Pin Description (Continued)
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
29
ATIGCLKC0
OUT Complementary clock of differential SRC clock pair.
30
ATIGCLKT0
OUT True clock of differential SRC clock pair.
31
GNDATI
PWR Ground for ATI Gclocks, nominal 3.3V
32
VDDATI
PWR Power supply ATI Gclocks, nominal 3.3V
33
SRCCLKC0
34
SRCCLKT0
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
35
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
36
GNDSRC
PWR Ground pin for the SRC outputs
37
IREF
This pin establishes the reference current for the differential current-mode
OUT output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
38
GNDA
PWR Ground pin for the PLL core.
39
VDDA
PWR 3.3V power for the PLL core.
40
CPUCLKC2_ITP
Complementary clock of differential pair CPU outputs. These are current mode
OUT _{outputs. External resistors are required for voltage bias.}
41
CPUCLKT2_ITP
OUT ^{True clock of differential pair CPU outputs. These are current mode outputs.}
External resistors are required for voltage bias.
42
CPUCLKC1
OUT ^{Complementary clock of differential pair CPU outputs. These are current mode}
outputs. External resistors are required for voltage bias.
43
CPUCLKT1
True clock of differential pair CPU outputs. These are current mode outputs.
OUT _{External resistors are required for voltage bias.}
44
GNDCPU
PWR Ground pin for the CPU outputs
45
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
46
CPUCLKC0
OUT ^{Complementary clock of differential pair CPU outputs. These are current mode}
outputs. External resistors are required for voltage bias.
47
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
48
*CPU_STOP#
IN Stops all CPUCLK, except those set to be free running clocks
49
GNDPCI
PWR Ground pin for the PCI outputs
FS Table select latch input pin / 3.3V PCI clock output.
50
**CK410#/PCICLK0
I/O _{0 = CK410 FS Table, 1 = CK409 FS Table}
51
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
52
**TEST_SEL/REF2
I/O 1 = All outputs are CK410 REF/N test mode
0 = All outputs behave normally.
53
**FS_B/REF1
54
**FS_A/REF0
55
GND
56
VDDREF
I/O Frequency select latch input pin / 14.318 MHz reference clock.
I/O Frequency select latch input pin / 14.318 MHz reference clock.
PWR Ground pin.
PWR Ref, XTAL power supply, nominal 3.3V
0891E—03/07/05
3