ICS93712 Datasheet, PDF (3/6 Pages) Integrated Circuit Systems – 2 DIMM DDR Fanout Buffer

ICS9371 2
Advance Information
Byte 5: Reserved Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
1 Reserved
Byte 6: Output Control
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
1 (Reserved)
Bit 6
-
0 (Reserved)
Bit 5
-
0 (Reserved)
Bit 4
-
0 (Reserved)
Bit 3
-
1 (Reserved)*
Bit 2 27, 26 1 DDRT5, DDRC5
Bit 1 23, 22 1 DDRT4, DDRC4
Bit 0 19, 18 1 DDRT3, DDRC3
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
12, 13
-
7, 8
-
3, 4
PWD
DESCRIPTION
1 Reserved*
1 Reserved*
1 Reserved*
1
DDRT2
DDRC2
1 Reserved*
1
DDRT1
DDRC1
1 Reserved*
1 DDRT0, DDRC0
Note:
* For lower power consumption, these bits should be driven to 0.
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
Maximum Operating Frequency
66
Input clock duty cycle
Output to Output Skew
Pulse skew
Duty cycle
Rise Time, Fall Time
d_tin
40
T_skew
T_skewp
D_C2
66MHz to 100MHz
101MHz to 167MHz
48
47
tr, tf
Load = 120Ω/16pF
650
Notes:
1. Refers to transition on noninverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t_wH/t_c, were the cycle (t_c)
decreases as the frequency goes up.
TYP MAX UNITS
200 MHz
60
%
100 ps
100 ps
52
%
53
%
950 ps
3