ICS93712 Datasheet, PDF (2/6 Pages) Integrated Circuit Systems – 2 DIMM DDR Fanout Buffer

Pin Descriptions
PIN NUMBER
PIN NAME
1
FB_OUT
5, 9, 14, 17, 21, 25 VDD2.5
2, 6, 11, 20, 24, 28 GND
27, 23, 19, 12, 7, 3 DDRT (5:0)
26, 22, 18, 13, 8, 4 DDRC (5:0)
10
BUF_IN
15
SDATA
16
SCLK
ICS9371 2
Advance Information
TYPE
DESCRIPTION
OUT Feedback output, dedicated for external feedback
PWR 2.5V voltage supply
PWR Ground
OUT "True" Clock of differential pair outputs.
OUT "Complementory" clocks of differential pair outputs.
IN Single ended buffer input
I/O Data pin for I²C circuitry 5V tolerant
IN Clock input of I²C input, 5V tolerant input
Byte 1: Reserved Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
1 Reserved
Byte 3: Reserved Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 2: Reserved Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
1 Reserved
Byte 4: Reserved Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
1 Reserved
2