ICS9160-03 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – Frequency Generator and Integrated Buffer for PowerPC

ICS9160-03
Preliminary Product Preview
Functionality
FS2
FS1
FS0
X1, REFCLK PCLK (0:3) BCLK (0:6) GRAPHIC
(MHz)
(MHKz)
(MHz)
(MHz)
FLOPPY
(MHz)
KEYBD
(MHz)
0*
0*
0*
Tristate
Tristate
Tristate
Tristate
Off
Tristate
0*
0*
1*
H/L*
Off
Off
H/L*
H/L*
H/L*
0
1
0
14.318
33.3
16.6
40.0
24.0
12.0
0
1
1
14.318
50.0
25.0
40.0
24.0
12.0
1
0
0
14.318
60.0
30.0
40.0
24.0
12.0
1
0
1
14.318
66.6
33.3
40.0
24.0
12.0
1
1
0
14.318
80.0
40.0
40.0
24.0
12.0
1
1
1
TCLK**
TCLK/2
TCLK/4
TCLK/3
TCLK/5
TCLK/10
* The oscillator and all PLLs are stopped to minimize power consumption in modes ‘000’ and ‘001.’ All outputs maintain
their last stable value in mode ‘001.’ Control signals STOP0 and STOP1 can be used to ensure glitch-free start and stop
when entering mode ‘001,’ provided mode ‘001’ is entered after the clocks have stopped and exited 10ms (maximum PLL
lock time) prior to starting clocks.
** X1 is externally driven with TCLK in mode ‘111.’
Group Clock Control
STOP1
+
0
0
1
1
STOP0
+
0
1
0
1
SDATA
*
1
1
1
1
PCLK (0:1)
Low
Low
Low
Running
PCLK (2:3)
Low
Low
Running
Running
BCLK (0;6)
Low
Running
Running
Running
GRAPHIC,
FLOPPY
Low
Running
Running
Running
KEYBD,
REFCLK
Running
Running
Running
Running
Outputs stop and start glitch-free within on-clock period. Outputs will not change state if the PLLs are off.
* Each output can be stopped and started glitch-free as described in the SDATA pin description above.
+SDATA control and STOP(0:1) control are logically ORed for each individual clock.
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