ICS85314-01 Datasheet, PDF (3/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85314-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
Q0:Q4
nQ0:nQ4
0
0
CLK0, nCLK0
Enabled
Enabled
0
1
CLK1
Enabled
Enabled
1
0
CLK0, nCLK0
Disabled; LOW
Disabled; HIGH
1
1
CLK1
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs as described
in Table 3B.
nCLK0
CLK0, CLK1
Disabled
Enabled
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1 - nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK0 or CLK1
nCLK0
Outputs
Q0:Q4
nQ0:nQ4
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
85314AG-01
www.icst.com/products/hiperclocks.html
3
REV. B JUNE 21, 2002