ICS85314-01 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85314-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.8V * 55mA = 209mW
• Power (outputs)_MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_{_MAX} (3.465V, with all outputs switching) = 209mW + 151mW = 360mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.360W * 66.6°C/W = 109°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE q_JA FOR 20-PIN TSSOP, FORCED CONVECTION
q_JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE q_JA FOR 20-PIN SOIC, FORCED CONVECTION
q_JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85314AG-01
www.icst.com/products/hiperclocks.html
10
REV. B JUNE 21, 2002