ICS84329-01B Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
M0, M1, M2, M3,
M4, M5, M6, M7, M8
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
N0, N1
Input
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
V_EE
TEST
Power
Output
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
V_CC
nFOUT, FOUT
Power
Output
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
S_CLOCK
Input
Pulldown
Clocks the serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
V_CCA
nc
Power
Unused
Analog supply pin.
No connect.
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
nP_LOAD
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into
the M divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84329BM-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 10, 2005