ICS84329-01B Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84329B-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by ad-
justing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a 50%
output duty cycle.
The programmable features of the ICS84329B-01 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift reg-
ister out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows: _fVCO
=
fxtal
16
x
M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 250 ≤ M ≤ 511. The frequency out is defined as
follows:
fout
=
fVCO
N
=
fxtal
16
x
M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits
and test bits T2:T0. The internal registers T2:T0 determine
the state of the TEST output as follows:
T2 T1 T0
TEST Output
fOUT
0
00
Shift Register Out
fOUT
0
01
High
fOUT
0
10
PLL Reference Xtal ÷ 16
fOUT
0
11
VCO ÷ M, (non 50% Duty M divider)
fOUT
1
0 0 fOUT, LVCMOS Output Frequency < 200MHz
fOUT
1
01
Low
fOUT
1
10
S_CLOCK ÷ M
(non 50% Duty Cycle M divider)
S_CLOCK ÷ N divider
1 11
fOUT ÷ 4
fOUT
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
tt
SH
nP_LOAD
M0:M8, N0:N1
t
S
PARALLEL LOADING
M, N
nP_LOAD
S_LOAD
84329BM-01
tt
SH
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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2
REV. A JUNE 10, 2005