ICS8430I-61 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
28, 29, 30
31, 32, 1, 2
3, 4
Name
M0, M1, M2
M3, M4, M5, M6
M7, M8
Type
Description
Input Pulldown _{M divider inputs. Data latched on LOW-to-HIGH transition of}
Input Pullup ^{nP_LOAD input. LVCMOS / LVTTL interface levels.}
5, 7
6
8, 16
9
10
11, 12
N0, N2
N1
V_EE
TEST
V_CC
FOUT1, nFOUT1
Input
Input
Power
Output
Power
Output
Pulldown _{Determines output divider value as defined in Table 3C,}
Pullup ^{Function Table. LVCMOS / LVTTL interface levels.}
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
13
14, 15
V_CCO
Power
FOUT0, nFOUT0 Output
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input Pulldown outputs nFOUTx to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
21
V_CCA
Power
Analog supply pin.
Selects between crystal oscillator or test inputs as the PLL
22
XTAL_SEL
Input Pullup reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24,
25
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8430AYI-61
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REV. A OCTOBER 21, 2004