ICS83940-01 Datasheet, PDF (3/11 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83940-01
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0
1
CLK0, nCLK0
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK-SEL LVCMOS_CLK
CLK0
nCLK0
Outputs
Q0 thru
Q17
Input to Output Mode
Polarity
0
—
0
1
LOW Differential to Single Ended Non Inverting
0
—
1
0
HIGH Differential to Single Ended Non Inverting
0
—
0
Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting
0
—
1
Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting
0
—
Biased; NOTE 1
0
HIGH Single Ended to Single Ended Inverting
0
—
Biased; NOTE 1
1
LOW Single Ended to Single Ended Inverting
1
0
—
—
LOW Single Ended to Single Ended Non Inverting
1
1
—
—
HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets
the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to
VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
VDDI/2.
83940AY-01
www.icst.com/products/hiperclocks.html
3
REV. A JULY 31, 2001