ICS620-01 Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – Digital Still Camera Clock Source

PRELIMINARY INFORMATION
ICS620-01
I C R O C LOC K ^{Digital Still Camera Clock Source}
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS
Minimum Typical Maximum Units
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS
Referenced to GND
Referenced to GND
-0.5
0
Max of 10 seconds
-65
7
V
VDD+0.5
V
70
°C
260
°C
150
°C
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Mid-level Voltage
Input Low Voltage, VIL
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
Operating Supply Current, IDD
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance
AC CHARACTERISTICS
3
5.5
V
Pins 6, 16, 20, 24, 27
2
V
Pins 6, 16, 20, 24, 27
0.8
V
Pins 1, 9, 28
VDD-0.5
V
Pins 1, 9, 28
Leave pin unconnected or tri-stated
V
Pins 1, 9, 28
0.5
V
IOH=-4mA
VDD-0.4
V
IOH=-25mA
2.4
V
IOL=25mA
0.4
V
No Load
TBD
mA
Each output
±70
mA
Pins 6, 16, 20, 24, 27
250
kΩ
All inputs but X1
7
pF
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Jitter
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
14.31818
MHz
TBD
ns
TBD
ns
45
49 to 51
55
%
TBD
ps
Note:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The ICS620-01 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on VDD pins 5, 7+8, and 21 to ground, as close to the ICS620-01 as possible. A series termination resistor of 33Ω should
be used for each clock output. The 14.31818 MHz crystal should be parallel resonant with an accuracy of 30ppm or better. For
tuning, the formula 2•(CL-6) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground,
where CL = the crystal load (or “correlation”) capacitance.
MDS 620-01 B
3
Revision 072098 Printed 12/4/00
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