ICS620-01 Datasheet, PDF (1/4 Pages) Integrated Circuit Systems – Digital Still Camera Clock Source

PRELIMINARY INFORMATION
ICS620-01
I C R O C LOC K ^{Digital Still Camera Clock Source}
Description
The ICS620-01 is a low cost, low jitter, high
performance clock synthesizer for digital still
cameras. Using analog Phase-Locked Loop
(PLL) techniques, the device uses a
14.318 MHz crystal input to produce multiple
output clocks required in the camera. It
provides selectable NTSC/PAL clock, a
selectable processor clock, a selectable CCD
clock, and a selectable interface clocks. Most
clocks are generated to a very low ppm
synthesis error rate.
All clocks can be turned off using a power
down mode. Custom versions with user-
defined frequencies and power down modes
are available in 6-8 weeks.
Features
• Packaged in 28 pin, 150 mil wide SSOP (QSOP)
• Provides all clocks necessary for many digital still
camera systems
• All clocks are frequency locked together
• Interface clock for USB, P1394, or UART
• Saves space over multiple crystals and oscillators
• Clocks power down when all select pins are low
• Full CMOS outputs also compatible with TTL levels
• +3.3 V or +5 V operation
• Low power, sub-micron CMOS process
• Custom versions available
Block Diagram
NSEL1:0
2
PSEL1:0
2
CSEL1:0
ISEL1:0
X1
X2
14.31818
MHz
crystal
2
2
Crystal
Oscillator
PLL Clock
Synthesis
Circuitry ÷2
PLL Clock
Synthesis
Circuitry _÷2
PLL Clock
Synthesis
Circuitry _÷2
PLL Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
NTSC/PAL Clock 1
NTSC/PAL Clock 2
Processor Clock 1
Processor Clock 2
CCD Clock 1
CCD Clock 2
Interface Clock 1
Interface Clock 2
MDS 620-01 B
1
Revision 072098 Printed 12/4/00
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