ICS571 Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer

PRELIMINARY INFORMATION
ICS571
Low Phase Noise Zero Delay Buffer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Output
Referenced to GND
Ambient Operating Temperature
Soldering Temperature
Max of 10 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK, FBIN
Pins 1, 8
Input Low Voltage, VIL, ICLK, FBIN
Pins 1, 8
Output High Voltage, VOH, CMOS level
IOH=-4mA
Output High Voltage, VOH
IOH=-25mA
Output Low Voltage, VOL
IOL=25mA
IDD Operating Supply Current, 133 in, 133 out No Load, 3.3V
IDD Operating Supply Current, 50 in, 100 out No Load, 3.3V
Short Circuit Current
Each Output
Input Capacitance, ICLK, FBIN
AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)
Input Frequency, clock input
FB from CLK
Input Frequency, clock input
FB from CLK/2
Skew CLK/2 with respect to CLK
Note 2
Input clock to output connected to FBIN
Note 2
Output Clock Rise Time, 5V
0.8 to 2.0V, 15 pF load
Output Clock Fall Time, 5V
2.0 to 0.8V, 15 pF load
Output Clock Rise Time, 3.3V
0.8 to 2.0V, 15 pF load
Output Clock Fall Time, 3.3V
2.0 to 0.8V, 15 pF load
Output Clock Duty Cycle, 5V
at VDD/2
Output Clock Duty Cycle, 3.3V
at VDD/2
Absolute Clock Period Jitter, CLK, note 3
Deviation from mean
One Sigma Clock Period Jitter, CLK, note 3
Phase Noise, relative to carrier
1kHz offset
Phase Noise, relative to carrier
100kHz offset
Minimum
-0.5
-0.5
0
-65
3
VDD/2+1
VDD-0.4
2.4
20
10
150
-500
40
45
Typical
VDD/2
VDD/2
34
26
±100
5
500
0.3
0.4
0.45
0.55
52 to 55
49 to 51
±80
50
-105
-115
Maximum
7
VDD+0.5
VDD+0.5
70
260
150
5.5
VDD/2-1
0.4
160
80
850
500
60
55
Notes:
1. Stresses beyond these can permanently damage the device.
2. Assumes clocks with same rise time, measured from rising edges at VDD/2. Measured with 33Ω
termination resistors and 15 pF loads. Applies to both 3.3V and 5V operation.
3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.
Units
V
V
V
°C
°C
°C
V
V
V
V
V
V
mA
mA
mA
pF
MHz
MHz
ps
ps
ns
ns
ns
ns
%
%
ps
ps
dBc/Hz
dBc/Hz
MDS 571 B
3
Revision 072899
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•[phone]tel•[phone]fax