ICS571 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer

PRELIMINARY INFORMATION
ICS571
Low Phase Noise Zero Delay Buffer
Pin Assignment
ICLK 1
VDD 2
GND 3
CLK/2 4
8 FBIN
7 CLK
6 VDD
5 GND
Feedback Configuration Table and Frequency Ranges (at 3.3V)
Feedback From
CLK
CLK/2
CLK
Input clock frequency Input clock frequency/2
CLK/2
2xInput clock frequency Input clock frequency
Input Range
20 -160 MHz
10 - 80 MHz
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
ICLK
VDD
GND
CLK/2
GND
VDD
CLK
FBIN
Type
CI
P
P
O
P
P
O
CI
Description
Reference clock input.
Connect to +3.3V or +5V. Must be same as other VDD.
Connect to ground.
Clock output per Table above. Low skew divide by two of pin 7 clock.
Connect to ground.
Connect to +3.3V or +5V. Must be same as other VDD.
Clock output per Table above.
Feedback clock input. Connect to CLK or CLK/2 per table above.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS571 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND on each
side of the chip (between pins 2 and 3, and also between pins 6 and 5). They must be connected close to
the ICS571 to minimize lead inductance. No external power supply filtering is required for this device.
A 33 Ω terminating resistor can be used next to each output pin.
MDS 571 B
2
Revision 072899
Printed 11/14/00
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