ICS554-01A Datasheet, PDF (3/6 Pages) Integrated Circuit Systems – LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

ICS554-01A
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
External Components
The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and
GND on pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should
be placed as close to the device as possible.
To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do
not, the output skew will be degraded. For example, using a 30Ω series termination on one output (with
33Ω on the others) will cause at least 15ps of skew.
Termination for PECL or LVPECL Outputs
The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two
different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs.
Therefore, termination resistors (DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50 ohm transmission lines. Matched impedance
techniques should be used to maximize operating frequency and minimize signal distortion. There are a
few simple termination schemes. The figures below show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist, but it is recommended that board designers
simulate to guarantee compatibility across all printed circuit and clock component process variations.
Z₀ = 50 ohms
F_OUT
Z₀ = 50 ohms
F_IN
50 ohms
50 ohms
C1
1
RTT = _{(VOH + VOL / VCC -2) -2} Z₀
C1 = 0.1µF to 0.01µF
RTT
PECL or LVPECL Output Termination
F_OUT
3.3 V
5 _{2 Z0}
Z₀ = 50 ohms
Z₀ = 50 ohms
3 _{2 Z0}
5 _{2 Z0}
F_IN
3 _{2 Z0}
LVPECL Output Termination
MDS 554-01A A
3
Revision 101904
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