ICS554-01A Datasheet, PDF (1/6 Pages) Integrated Circuit Systems – LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

ICS554-01A
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Description
The ICS554-01A is a low skew clock buffer with a
single complimentary PECL input to four PECL
outputs. Part of ICS’ Clock Blocks^TM family, this is our
lowest skew PECL clock buffer. The ICS554-01A is
footprint compatible with the ICS554-01, but requires
fewer passive components for termination thus
providing a cost-saving alternative. For parts which do
not require PECL inputs or outputs, see the ICS553 for
a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8
low skew buffer. For more than 8 outputs see the
MK74CBxxx Buffalo^TM series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
• Input frequency up to 200 MHz
• Advanced CMOS process
• Outputs are skew matched to within 50 ps
• Packaged in 16-pin TSSOP
• One PECL input to 4 PECL output clock drivers
• Operating Voltages of 3.3 V or 5 V
• Industrial temperature range
• Functional equivalent to ICS554-01
• Simplified passive termination network compared to
ICS554-01
Block Diagram
IN
IN
VDD
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VSS
MDS 554-01A A
1
Revision 101904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com