ICS542 Datasheet, PDF (3/4 Pages) Integrated Circuit Systems – Clock Divider

ICS542
Clock Divider
Electrical Specifications
Parameter
Conditions
Minimum Typical
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Output
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1 VDD/2
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
Input High Voltage, VIH
S0, S1, OE
2
Input Low Voltage, VIL
S0, S1, OE
Output High Voltage, VOH, CMOS levels
IOH=-4mA
VDD-0.4
Output High Voltage, VOH
IOH=-12mA
2.4
Output Low Voltage, VOL
IOL=4mA
IDD Operating Supply Current, 100 MHz input No Load, 5.0V, 11 sel
11
IDD Operating Supply Current, 100 MHz input No Load, 3.3V, 11 sel
7
Short Circuit Current
Each Output
±40
Input Capacitance, S1, S0, OE
Pins 4, 5, 6
4
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, clock input
at VDD = 5V
0
Input Frequency, clock input
at VDD = 3.3V
0
Skew of output clocks
rising edges at VDD/2
Output Clock Rise Time
0.8 to 2.0V
1
Output Clock Fall Time
2.0 to 0.8V
1
Output Clock Duty Cycle
at VDD/2
45
49 to 51
Maximum
7
VDD+0.5
VDD+0.5
70
260
150
5.5
(VDD/2)-1
0.8
0.4
156
156
500
55
Units
V
V
V
C
C
C
V
V
V
V
V
V
V
V
mA
mA
mA
pF
MHz
MHz
ps
ns
ns
%
MDS 542 B
3
Revision 050400
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• [phone]tel • www.icst.com