ICS542 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – Clock Divider

ICS542
Clock Divider
Pin Assignment
ICLK
VDD
GND
S0
1
8
2
7
3
6
4
5
8 pin SOIC
CLK
CLK/2
OE
S1
Clock Decoding Table
S1 S0 CLK CLK/2
0 0 Power Down All
0 1 Input/6 Input/12
1 0 Input/8 Input/16
1 1 Input/2 Input/4
0 = connect directly to ground.
1 = connect directly to VDD.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
ICLK
VDD
GND
S0
S1
OE
CLK/2
CLK
Type
CI
P
P
I
I
I
O
O
Description
Clock input.
Connect to +3.3V or +5V.
Connect to ground.
Select 0 for output clock. Connect to GND or VDD. Internal pull-up.
Select 1 for output clock. Connect to GND or VDD. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
Clock output per Table above. Low skew divide by two of pin 8 clock.
Clock output per Table above.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS542 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS542 to minimize lead inductance. No external power supply filtering is
required for this device. A 33 Ω series terminating resistor can be used next to each output pin. If a 3.3 V
input clock is applied to the ICLK pin, with the ICS542 at 5 V, the clock must be AC coupled.
MDS 542 B
2
Revision 050400
Printed 11/14/00
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