9DBU0931 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0931 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSADR_tri
2 vOE8#
3 DIF8
4 DIF8#
5 VDDR1.5
6 CLK_IN
7 CLK_IN#
8 GNDR
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.5
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD1.5
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA1.5
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD1.5
39 VDDIO
40 GND
TYPE
DESCRIPTION
LATCHED _{Tri-level latch to select SMBus Address. See SMBus Address Selection Table.}
IN
IN
Active low input for enabling DIF pair 8. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR ^{1.5V power for differential input clock (receiver). This VDD should be treated as}
an Analog power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Analog Ground pin for the differential input (receiver)
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.5V digital power (dirty power)
PWR Power supply for differential outputs
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
GND Ground pin.
REVISION C 04/22/15
3
9 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER